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tc59lm914/06amg-37,-50 2004-08-20 1/59 rev 1.0 tentative toshiba mos digital integr ated circuit silicon monolithic 512mbits network fcram1 (sstl_18 / hstl_interface) ? 4,194,304-words 8 banks 16-bits ? 8,388,608-words 8 banks 8-bits description network fcram tm is double data rate fast cycle random access memory. tc59lm914/06amg is fast cycle random access memory (network fcram tm ) containing 536,870,912 memory cells. TC59LM914AMG is organized as 4,194,304-words 8 banks 16 bits, tc59lm906amg is organized as 8,388,608-words 8 banks 8 bits. tc59lm914/06amg feature a fully synchronous operation re ferenced to clock edge whereby all operations are synchronized at a clock in put which enables high performance and simple user interf ace coexistence. tc59lm914/06amg can operate fast core cycle compared with regular ddr sdram. tc59lm914/06amg is suitable for network, server and ot her applications where large memory density and low power consumption are re quired. the output dr iver for network fcram tm is capable of high quality fast data transfer under light loading condition. features tc59lm914/06 parameter -37 -50 cl = 3 5.5 ns 6.0 ns cl = 4 4.5 ns 5.5 ns t ck clock cycle time (min) cl = 5 3.75 ns 5.0 ns t rc random read/write cycle time (min) 22.5 ns 27.5 ns t rac random access time (max) 22.0 ns 24.0 ns i dd1s operating current (singl e bank) (max) 280 ma 240 ma l dd2p power down current (max) 90 ma 80 ma l dd6 self-refresh current (max) 20 ma 20 ma ? fully synchronous operation ? double data rate (ddr) data input/output are synchroniz ed with both edges of dqs. ? differential clock (clk and clk ) inputs cs , fn and all address input signals are sampled on the positive edge of clk. output data (dqs and dqs) is aligned to the crossings of clk and clk . ? fast clock cycle time of 3.75 ns minimum clock: 266 mhz maximum data: 533 mbps/pin maximum ? fast cycle and short latency ? eight independent banks operation when ba2 input assign to a14 input, tc59lm914/06amg can function as 4 bank device (keep backward compatibility to 256mb) ? bidirectional differential data strobe signal : tc59lm906amg ? bidirectional data strobe signal per byte : TC59LM914AMG ? distributed auto-refresh cycle in 3.9 s ? self-refresh ? power down mode ? variable write length control ? write latency = cas latency-1 ? programable cas latency and burst length cas latency = 3, 4, 5 burst length = 2, 4 ? organization: TC59LM914AMG : 4,194,304 words 8 banks 16 bits tc59lm906amg : 8,388,608 words 8 banks 8 bits ? power supply voltage v dd : 2.5 v 0.125v v ddq : 1.4 v 1.9 v ? 1.8 v cmos i/o comply with sstl_18 and hstl ? package: 60ball bga, 1mm 1mm ball pitch (p ? bga64 ? 1317 ? 1.00az) notice : fcram is trademark of fujitsu limited, japan.
tc59lm914/06amg-37,-50 2004-08-20 2/59 rev 1.0 tc59lm906amg pin names pin name pin name a0~a13 address input dqs / dqs write/read data strobe ba0~ba2 bank address v dd power ( + 2.5 v) dq0~dq7 data input / output v ss ground cs chip select v ddq power ( + 1.5 v / + 1.8 v) (for i/o buffer) fn function control v ssq ground (for i/o buffer) pd power down control v ref reference voltage clk, clk clock input nc not connected 4 bank operation can be performed using ba2 as a14. pin assignment (top view) : depopulated ball ball pitch=1.0 x 1.0mm 5 a b c d e f g h j k 1 3 6 4 2 x 8 l m n p r nc nc nc nc v dd nc dq1 nc nc dq3 nc nc ba2 a13 nc ba0 a10 a1 v dd v ss nc dq6 nc nc dq4 nc nc vref clk a12 a11 a8 a5 v ss dq7 v ss q v dd q dq5 v ss q v dd q v ss q v ss clk pd a9 a7 a6 a4 dq0 v dd q v ss q dq2 v dd q v ss q v dd q v dd fn cs ba1 a0 a2 a3 dqs dqs inde x
tc59lm914/06amg-37,-50 2004-08-20 3/59 rev 1.0 TC59LM914AMG pin names pin name pin name a0~a13 address input udqs/ldqs write/read data strobe ba0~ba2 bank address v dd power ( + 2.5 v) dq0~dq15 data input / output v ss gorund cs chip select v ddq power ( + 1.5 v / + 1.8 v) (for i/o buffer) fn function control v ssq power (for i/o buffer) pd power down control v ref reference voltage clk, clk clock input nc not conneted 4 bank operation can be performed using ba2 as a14. pin assignment (top view) : depopulated ball ball pitch=1.0 x 1.0mm 5 a b c d e f g h j k 1 3 6 4 2 x 16 l m n p r nc nc nc nc v dd dq1 dq2 dq3 dq5 dq6 dq7 nc ba2 a13 nc ba0 a10 a1 v dd v ss dq14 dq13 dq12 dq10 dq9 dq8 nc vref clk a12 a11 a8 a5 v ss dq15 v ss q v dd q dq11 v ss q v dd q v ss q v ss clk pd a9 a7 a6 a4 dq0 v dd q v ss q dq4 v dd q v ss q v dd q v dd fn cs ba1 a0 a2 a3 ldqs udqs inde x
tc59lm914/06amg-37,-50 2004-08-20 4/59 rev 1.0 block diagram note: the tc59lm906amg configuration is 8 banks of 16384 512 8 of cell array with the dq pins numbered dq0~dq7. the TC59LM914AMG configuration is 8 banks of 16384 256 16 of cell array with the dq pins numbered dq0~dq15. tc59lm906amg has dqs, dqs pin for differential data strobe. TC59LM914AMG has udqs and ldqs. dq0~dqn dll clock buffer cl k clk pd to each block command decoder cs fn address buffer control signal generator mode register refresh counter a0~a13 ba0~ba2 burst counter write address latch/ address comparator data control and latch circuit upper address latch read data buffer dq buffer dqs lower address latch dqs write data buffer bank #7 bank #6 bank #5 bank #4 bank #3 bank #2 bank #1 bank #0 memory cell array column decoder row decoder
tc59lm914/06amg-37,-50 2004-08-20 5/59 rev 1.0 absolute maximum ratings symbol parameter rating unit notes v dd power supply voltage ? 0.3~ 3.3 v v ddq power supply voltage (for i/o buffer) ? 0.3~v dd + 0.3 v v in input voltage ? 0.3~v dd + 0.3 v v out output and i/o pin voltage ? 0.3~v ddq + 0.3 v v ref input reference voltage ? 0.3~v dd + 0.3 v t opr operating temperature (case) 0~85 c t stg storage temperature ? 55~150 c t solder soldering temperature (10 s) 260 c p d power dissipation 2 w i out short circuit output current 50 ma caution: conditions outside the limits listed under ?absolute m aximum ratings? may cause permanent damage to the device. the device is not meant to be operated under conditions outside the limits descri bed in the operational section of this specification. exposure to ?absolute maximum ratings? conditions for extended periods may af fect device reliability. recommended dc, ac operating conditions (notes: 1)(t case = 0~85c) symbol parameter min typ. max unit notes v dd power supply voltage 2.375 2.5 2.625 v v ddq power supply voltage (for i/o buffer) 1.4 ? 1.9 v v ref input reference voltage v ddq /2 95% v ddq /2 v ddq /2 105% v 2 v ih (dc) input dc high voltage v ref + 0.125 ? v ddq + 0.2 v 5 v il (dc) input dc low voltage ? 0.1 ? v ref ? 0.125 v 5 v ick (dc) differential dc input voltage ? 0.1 ? v ddq + 0.1 v 10 v id (dc) input dc differential voltage. 0.4 ? v ddq + 0.2 v 7, 10 v ih (ac) input ac high voltage v ref + 0.2 ? v ddq + 0.2 v 3, 6 v il (ac) input ac low voltage ? 0.1 ? v ref ? 0.2 v 4, 6 v id (ac) input ac differential voltage 0.5 ? v ddq + 0.2 v 7, 10 v x (ac) differential ac input cross point voltage v ddq /2 ? 0.125 ? v ddq /2 + 0.125 v 8, 10 v iso (ac) differential ac middle level v ddq /2 ? 0.125 ? v ddq /2 + 0.125 v 9, 10
tc59lm914/06amg-37,-50 2004-08-20 6/59 rev 1.0 note: (1) all voltages referenced to v ss , v ssq . (2) v ref is expected to track variations in v ddq dc level of the transmitting device. peak to peak ac noise on v ref may not exceed 2% v ref (dc). (3) overshoot limit: v ih (max) = v ddq + 0.7 v with a pulse width 5 ns. (4) undershoot limit: v il (min) = ? 0.7 v with a pulse width 5 ns. (5) v ih (dc) and v il (dc) are levels to mainta in the current logic state. (6) v ih (ac) and v il (ac) are levels to change to the new logic state. (7) v id is magnitude of the difference between v tr input level and v cp input level. (8) the value of v x (ac) is expected to equal v ddq /2 of the transmitting device. (9) v iso means {v ick (v tr ) + v ick (v cp )} /2. (10) refer to the figure below. vtr is the true inpu t (such as clk, dqs) level an d vcp is the complementary input (such as clk , dqs ) level. (11) in the case of external termination, vtt (termination voltage) should be gone in the range of v ref (dc) 0.04 v. capacitance (v dd = 2.5v , v ddq = 1.8 v, f = 1 mhz, ta = 25c) symbol parameter min max delta unit c in input pin capacitance 1.5 2.5 0.25 pf c inc clock pin (clk, clk ) capacitance 1.5 2.5 0.25 pf c i/o dq, dqs, udqs, ldqs, dqs capacitance 2.5 4 0.5 pf c nc nc pin capacitance ? 4 ? pf note: these parameters are periodi cally sampled and not 100% tested. v iso ( min ) v iso ( max ) v ick v ick v x v x v x v x v x v ick v ick cl k clk v ss |v id (ac)| 0 v differential v iso v ss v id (ac)
tc59lm914/06amg-37,-50 2004-08-20 7/59 rev 1.0 recommended dc operating conditions (v dd = 2.5v 0.125v, v ddq = 1.4v ~ 1.9v, t case = 0~85c) max symbol parameter -37 -50 unit notes i dd1s operating current t ck = min, i rc = min ; read/write command cycling ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; 1 bank operation, burst length = 4 ; address change up to 2 times during minimum i rc . 280 240 1, 2 i dd2n standby current t ck = min, cs = v ih , pd = v ih ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; all banks: inactive state ; other input signals are changed one time during 4 t ck . 120 100 1, 2 i dd2p standby (power down) current t ck = min, cs = v ih , pd = v il (power down) ; 0 v v in v ddq ; all banks: inactive state 90 80 1, 2 i dd4w write operating current (4 banks) 8 bank interleaved continuos burst wirte operation ; t ck = min, i rc = min burst length = 4, cas latency = 5 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; address inputs change once per clock cycle ; dq and dqs inputs change twice per clock cycle. 450 350 1, 2 i dd4r read operating current (4 banks) 8 bank interleaved continuos burst wirte operation ; t ck = min, i rc = min, i out = 0ma ; burst length = 4, cas latency = 5 ; 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; address inputs change once per clock cycle ; read data change twice per clock cycle. 450 350 1, 2 i dd5b burst auto refresh current refresh command at every i refc at interval ; t ck = min z i refc = min cas latency = 5 0 v v in v il (ac) (max), v ih (ac) (min) v in v ddq ; address inputs change up to 2 times during minimum i refc. dq and dqs inputs change twice per clock cycle. 280 250 1, 2, 3 i dd6 self-refresh current self-refresh mode pd = 0.2 v, 0 v v in v ddq 20 20 ma 2 notes: 1. these parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t ck , t rc and i rc . 2. these parameters define the current between v dd and v ss . 3. i dd5b is specified under burst refresh condition. actual system should us e distributed refresh that meet t refi specification.
tc59lm914/06amg-37,-50 2004-08-20 8/59 rev 1.0 recommended dc operating conditions (continued) (v dd = 2.5v 0.125v, v ddq = 1.4v ~ 1.9v, t case = 0~85c) symbol parameter min max unit notes i li input leakage current ( 0 v v in v ddq , all other pins not under test = 0 v) ? 5 5 a i lo output leakage current (output disabled, 0 v v out v ddq ) ? 5 5 a i ref v ref current ? 5 5 a i oh (dc) v oh = 1.420v ? 5.6 ? i ol (dc) normal output driver v ol = 0.280v 5.6 ? i oh (dc) v oh = 1.420v ? 9.8 ? i ol (dc) strong output driver v ol = 0.280v 9.8 ? i oh (dc) v oh = 1.420v ? 2.8 ? i ol (dc) weak output driver v ol = 0.280v 2.8 ? 1 i oh (dc) v oh = 1.420v ? 13.4 ? i ol (dc) full strength output driver output source dc current (v ddq = 1.7v ~ 1.9v) v ol = 0.280v 13.4 ? ma 1, 2 i oh (dc) v oh = v ddq ? 0.4v ? 4 ? i ol (dc) normal output driver v ol = 0.4v 4 ? i oh (dc) v oh = v ddq ? 0.4v ? 8 ? i ol (dc) strong output driver v ol = 0.4v 8 ? i oh (dc) not defined ? ? i ol (dc) weak output driver not defined ? ? 1 i oh (dc) v oh = v ddq ? 0.4v ? 10 ? i ol (dc) full strength output driver output source dc current (v ddq = 1.4v ~ 1.6v) v ol = 0.4v 10 ? ma 1, 2 notes: 1. refer to output driver characteristics for the deta il. output driver strength is selected by extended mode register. 2. in case of full strength output driver, ocd calibrati on (off chip driver impedance adjustment) can be used. the specification of full strength output driver defines the default value after power-up.
tc59lm914/06amg-37,-50 2004-08-20 9/59 rev 1.0 ac characteristics and operating conditions (notes: 1, 2) -37 -50 symbol parameter min max min max unit notes t rc random cycle time 22.5 ? 27.5 ? 3 c l = 3 5.5 8.5 6.0 8.5 3 c l = 4 4.5 8.5 5.5 8.5 3 t ck clock cycle time c l = 5 3.75 8.5 5.0 8.5 3 t rac random access time ? 22.0 ? 24 3 t ch clock high time 0.45 t ck ? 0.45 t ck ? 3 t cl clock low time 0.45 t ck ? 0.45 t ck ? 3 t ckqs dqs access time from clk ? 0.45 0.45 ? 0.6 0.6 3,8,10 t qsq data output skew from dqs ? 0.25 ? 0.35 4 t ac data access time from clk ? 0.5 0.5 ? 0.65 0.65 3,8,10 t oh data output hold time from clk ? 0.5 0.5 ? 0.65 0.65 3, 8 t qspre dqs (read) preamble pulse width 0.9 t ck 1.1 t ck 0.9 t ck 1.1 t ck 3, 8 t hp clk half period (minimum of actual t ch , t cl ) min(t ch , t cl ) ? min(t ch , t cl ) ? 3 t qsp dqs (read) pulse width t hp ? t qhs ? t hp ? t qhs ? 4, 8 t qsqv data output valid time from dqs t hp ? t qhs ? t hp ? t qhs ? 4, 8 t qhs dq, dqs hold skew factor ? 0.055 t ck +0.17 ? 0.055 t ck +0.17 t dqss dqs (write) low to high setup time 0.75 t ck 1.25 t ck 0.75 t ck 1.25 t ck 3 t dspre dqs (write) preamble pulse width 0.25 t ck ? 0.25 t ck ? 4 t dspres dqs first input setup time 0 ? 0 ? 3 t dspreh dqs first low input hold time 0.25 t ck ? 0.25 t ck ? 3 t dsp dqs high or low input pulse width 0.35 t ck 0.65 t ck 0.35 t ck 0.65 t ck 4 c l = 3 0.75 ? 1.0 ? 3, 4 c l = 4 0.75 ? 1.0 ? 3, 4 t dss dqs input falling edge to clock setup time c l = 5 0.75 ? 1.0 ? 3, 4 t dsh dqs input falling edge hold time from clk 0.55 ? 0.75 ? 3, 4 t dspst dqs (write) postamble pulse width 0.4 t ck ? 0.4 t ck ? 4 c l = 3 0.75 ? 1.0 ? 3, 4 c l = 4 0.75 ? 1.0 ? 3, 4 t dspsth dqs (write) postamble hold time c l = 5 0.75 ? 1.0 ? 3, 4 t dssk udqs ? ldqs skew ( 16) ? 0.5 t ck 0.5 t ck ? 0.5 t ck 0.5 t ck t ds data input setup time from dqs 0.35 ? 0.45 ? 4 t dh data input hold time from dqs 0.35 ? 0.45 ? 4 t is command/address input setup time 0.5 ? 0.7 ? 3 t ih command/address input hold time 0.5 ? 0.7 ? ns 3
tc59lm914/06amg-37,-50 2004-08-20 10/59 rev 1.0 ac characteristics and operating conditions (notes: 1, 2) (continued) -37 -50 symbol parameter min max min max unit notes t lz data-out low impedance time from clk ? 0.5 ? ? 0.65 ? 3,6,8 t hz data-out high impedance time from clk ? 0.5 ? 0.65 3,7,8 t qslz dqs-out low impedance time from clk ? 0.5 ? ? 0.65 ? 3,6,8 t qshz dqs-out high impedance time from clk ? 0.5 0.5 ? 0.65 0.65 3,7,8 t qpdh last output to pd high hold time 0 ? 0 ? t pdex power down exit time 0.6 ? 0.8 ? 3 t t input transition time 0.1 1 0.1 1 t fpdl pd low input window for self-refresh entry ? 0.5 t ck 5 ? 0.5 t ck 5 3 t oit ocd drive mode output delay time 0 12 0 12 ns t refi auto-refresh average interval 0.4 3.9 0.4 3.9 5 t pause pause time after power-up 200 ? 200 ? s c l = 3 5 ? 5 ? c l = 4 5 ? 5 ? i rc random read/write cycle time (applicable to same bank) c l = 5 6 ? 6 ? i rcd rda/wra to lal command input delay (applicable to same bank) 1 1 1 1 c l = 3 4 ? 4 ? c l = 4 4 ? 4 ? i ras lal to rda/wra command input delay (applicable to same bank) c l = 5 5 ? 5 ? i rbd random bank access delay (applicable to other bank) 2 ? 2 ? b l = 2 2 ? 2 ? i rwd lal following rda to wra delay (applicable to other bank) b l = 4 3 ? 3 ? i wrd lal following wra to rda delay (applicable to other bank) 1 ? 1 ? c l = 3 5 ? 5 ? c l = 4 5 ? 5 ? i rsc mode register set cycle time c l = 5 6 ? 6 ? i pd pd low to inactive state of input buffer ? 1 ? 1 i pda pd high to active state of input buffer ? 1 ? 1 c l = 3 15 ? 15 ? c l = 4 18 ? 18 ? i pdv power down mode valid from ref command c l = 5 22 ? 22 ? c l = 3 15 ? 15 ? c l = 4 18 ? 18 ? i refc auto-refresh cycle time c l = 5 22 ? 22 ? i ckd ref command to clock input disable at self-refresh entry i refc ? i refc ? i lock dll lock-on time (applicable to rda command) 200 ? 200 ? cycle
tc59lm914/06amg-37,-50 2004-08-20 11/59 rev 1.0 ac test conditions symbol parameter value unit notes v ih (min) input high voltage (minimum) v ref + 0.2 v v il (max) input low voltage (maximum) v ref ? 0.2 v v ref input reference voltage v ddq /2 v v tt termination voltage v ref v v swing input signal peak to peak swing 0.7 v vr differential clock input reference level v x (ac) v v id (ac) input differential voltage 1.0 v slew input signal minimum slew rate 2.5 v/ns v otr output timing measurement reference voltage v ddq /2 v 9 note: (1) transition times are measured between v ih min (dc) and v il max (dc). transition (rise and fall) of input signals have a fixed slope. (2) if the result of nominal calculation with regard to t ck contains more than one de cimal place, the result is rounded up to the nearest decimal place. (i.e., t dqss = 0.75 t ck , t ck = 5 ns, 0.75 5 ns = 3.75 ns is rounded up to 3.8 ns.) (3) these parameters are measured fr om the differential clock (clk and clk ) ac cross point. (4) these parameters are measured from signal transition point of dqs crossing v ref level. in case of dqs enable mode, these parameters are measu red from the crossing point of dqs and dqs . (5) the t refi (max) applies to equally distributed refresh method. the t refi (min) applies to both burst refresh method and distributed refresh method. in such case, the average interval of eight consecutive auto-refresh commands has to be more than 400 ns always. in other words, the number of auto-refresh cycles which can be performed within 3.2 s (8 400 ns) is to 8 times in the maximum. (6) low impedance state is specified at v ddq /2 0.2 v from steady state. (7) high impedance state is specified wh ere output buffer is no longer driven. (8) these parameters depend on the clock jitter. these parameters are measured at stable clock. (9) output timing is measured by using normal driver strength at v ddq = 1.7v 1.9v. output timing is measured by using strong driver strength at v ddq = 1.4v 1.6v. (10) these parameters are measured at t ck = minimum 6.0ns. when t ck is longer than 6.0ns, these parameters are specified as below for all speed version t ckqs (min/max) = ? 0.6ns / 0.6ns, t ac (min/max) = ? 0.65ns / 0.65ns slew = (v ih min (ac) ? v il max (ac))/ ? t v ih min (ac) ? t v ref v il max (ac) v swing ? t v ss v ddq ac test load measurement point output v tt 25 ?
tc59lm914/06amg-37,-50 2004-08-20 12/59 rev 1.0 power up sequence (1) as for pd , being maintained by the low state ( 0.2 v) is desirable before a power-supply injection. (2) apply v dd before or at the same time as v ddq . (3) apply v ddq before or at the same time as v ref . (4) start clock (clk, clk ) and maintain stable condition for 200 s (min). (5) after stable power and clock, apply desl and take pd =h. (6) issue emrs to enable dll and to define driver strength with ocd calibration mode exit command (a7 a9 = 0). (note: 1, 2) (7) issue mrs for set cas latency (cl), burst type (bt), and burst length (bl). (note: 1) (8) issue two or more auto-refresh commands (note: 1). (9) ready for normal operation after 200 clocks from extended mode register programming. (10) if ocd calibration (off chip driver impedance ad justment) is used, execute ocd calibration sequence. notes: (1) sequence 6, 7 and 8 can be issued in random order. (2) set dqs mode for tc59lm906amg. (3) l = logic low, h = logic high (4) all dqs output level are high impedance state during power up sequence. command clk dq address v dd v ddq v ref clk pd 2.5v ( typ ) 1.5v or 1.8v ( typ ) 1/2 v ddq (typ) 200us ( min ) t pdex l pda l rsc l rsc l refc l refc 200clock c y cle ( min ) desl rda mrs desl rda mrs desl wra ref desl wra ref desl op-code emrs op-code mrs hi-z dqs emrs mrs auto refresh cycle normal operation hi-z dqs
tc59lm914/06amg-37,-50 2004-08-20 13/59 rev 1.0 timing diagrams input timing timing of the clk, clk t t t ck clk v ih v il v ih v il t cl t ch t t v ih (ac) v il (ac) clk clk clk v x v x v x v id (ac) t ih t is t ih t ck t cl t ch cs cl k clk t ck 1st 2nd t is t ih t is t ih 1st 2nd t ih t is t ih ua, ba la t is t is fn a0~a13 ba0 ba2 command and address dq (input) t ds t dh t ds t dh dqs dqs data ? tc59lm906amg dqs enable mode dq (input) refer to the command truth table. t ds t dh t ds t dh dqs data ? tc59lm906amg dqs disable mode ? TC59LM914AMG
tc59lm914/06amg-37,-50 2004-08-20 14/59 rev 1.0 read timing (burst length = 4) clk inpu t (control & addresses) dqs/ dqs (output) dq (output) cas latency = 3 dqs/ dqs (output) dq (output) cas latency = 4 dqs/ dqs (output) dq (output) cas latency = 5 hi-z lal (after rda) t is t ih hi-z t ch t cl t ck hi-z hi-z t qslz t qspre t ckqs t ckqs t qsp t qsp t ckqs t qshz t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac preamble postamble t qslz t qspre t ckqs t ckqs t qsp t qsp t ckqs t qshz preamble postamble q0 q1 q2 q3 t qsq t qsq t qsqv t qsqv t qsq t hz t lz t oh t ac t ac t ac q0 q1 q2 q3 t qslz t qspre t ckqs t ckqs t qsp t qsp t ckqs t qshz preamble postamble t qsq t qsq t qsqv t qsqv t qsq t hz t lz t ac t ac t ac q0 q1 q2 q3 hi-z hi-z desl cl k note: TC59LM914AMG doesn?t have dqs . the correspondence of ldqs, udqs to dq. (TC59LM914AMG) ldqs dq0 dq7 udqs dq8 dq15 dqs is hi-z in dqs disable mode. dqs mode is chosen by emrs. (tc59lm906amg) when dqs is enable, the condition of dqs is changed from hi-z to ?high at preamble and the condition of dqs is changed from ?high? to hi-z at postamble. t oh t qsq t ac
tc59lm914/06amg-37,-50 2004-08-20 15/59 rev 1.0 write timing (burst length = 4) dq (input) dqs/ dqs (input) dq (input) cas latency = 4 dqs/ dqs (input) cas latency = 3 t dspre t ds t dh d0 d1 t ds t dh d3 t ds t dh t dss t dqss t dspreh t dsp t dsp t ds preamble postamble t dsp t dqs t dspres t dspst t dspsth t dh t ds t dh t ds t dh t dss t dqs t dspreh t dsp t dsp preamble postamble t dsp t dss t dspres t dspst t dss t dspsth t dqss cl k clk inpu t (control & addresses) lal (after wra) t is t ih t ch t cl t ck t dspre dqs/ dqs (input) dq (input) cas latency = 5 t dspre t dss t dspreh t dsp t dsp t ds preamble postamble t dsp t dqss t dspres t dspst t dspsth t dh d0 d1 t ds t dh d3 t ds t dh t dss t dqss desl d2 d0 d1 d2 d3 d2 note: TC59LM914AMG doesn?t have dqs . the correspondence of ldqs, udqs to dq. (TC59LM914AMG) ldqs dq0 dq7 udqs dq8 dq15 dqs is ignored in dqs disable mode. dqs mode is chosen by emrs. (tc59lm906amg)
tc59lm914/06amg-37,-50 2004-08-20 16/59 rev 1.0 t refi , t pause , ixxxx timing cl k clk inpu t (control & addresses) command t is t ih note: ?i xxxx ? means ?i rc ?, ?i rcd ?, ?i ras ?, etc. t refi , t pause , i xxxx command t is t ih
tc59lm914/06amg-37,-50 2004-08-20 17/59 rev 1.0 write timing (x16 device) (burst length =4) cl k clk inpu t (control & addresses) ldqs dq0~dq7 cas latency = 3 udqs dq8~dq15 ldqs dq0~dq7 cas latency = 4 udqs dq8~dq15 preamble lal wra t ds t dssk t dh d0 d1 t ds t dh d2 d3 t ds t dh t ds preamble postamble t dh d0 d1 t ds t dh d2 d3 t ds t dh t ds t dh t dssk t dssk t dssk t dh t ds t ds t dssk d0 d1 t ds t dh d2 d3 t ds t dh t ds preamble d0 d1 t ds t dh d2 d3 t ds t dh t ds t dh t dssk t dssk t dssk t ds desl postamble postamble t dh ldqs dq0~dq7 cas latency = 5 udqs dq8~dq15 postamble t ds preamble t dssk t dh d0 d1 t ds t dh d2 d3 t ds t dh t ds preamble d0 d1 t ds t dh d2 d3 t ds t dh t ds t dh t dssk t dssk t dssk t ds postamble t dh t dh t dh postamble preamble t dh
tc59lm914/06amg-37,-50 2004-08-20 18/59 rev 1.0 function truth table (notes: 1, 2, 3) command truth table (notes: 4) ? the first command symbol function cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 desl device deselect h rda read with auto-close l h ba ua ua ua ua wra write with auto-close l l ba ua ua ua ua ? the second command (the next clock of rda or wra command) symbol function cs fn ba1~ ba0 ba2 a13 a12~ a11 a10~a 9 a8 a7 a6~a0 lal lower address latch (x16) h v v v la la lal lower address latch (x8) h v v la la la ref auto-refresh l mrs mode register set l v l l l l l v v notes: 1. l = logic low, h = logic high, = either l or h, v = valid (specified value), ba = bank address, ua = upper address, la = lower address 2. all commands are assumed to issue at a valid state. 3. all inputs for command (excluding selfx and pdex) are latche d on the crossing point of diff erential clock input where clk goes to high. 4. operation mode is decided by the combination of 1st command and 2nd command. refer to ?state diagram? and the command table below. read command table command (symbol) cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 notes rda (1st) l h ba ua ua ua ua lal (2nd) h la la la 5 note 5 : for x16 device, a8 is ?x? (either l or h). write command table ? TC59LM914AMG command(symbol) cs fn ba1~ ba0 ba2 a13 a12 a11 a10~ a9 a8 a7 a6~a0 wra (1st) l l ba ua ua ua ua ua ua ua ua lal (2nd) h lvw0 lvw1 uvw0 uvw1 la la ? tc59lm906amg command(symbol) cs fn ba1~ ba0 ba2 a13 a12 a11 a10~ a9 a8 a7 a6~a0 wra (1st) l l ba ua ua ua ua ua ua ua ua lal (2nd) h vw0 vw1 la la la notes: 6. ba2, a13 a11 are used for variable write length (vw) control at write operation.
tc59lm914/06amg-37,-50 2004-08-20 19/59 rev 1.0 function truth table (continued) vw truth table burst length function vw0 vw1 write all words l bl=2 write first one word h reserved l l write all words h l write first two words l h bl=4 write first one word h h note 7 : for x16 device, lvw0 and lvw1 control dq0~dq7. uvw0 and uvw1 control dq8~dq15. mode register set command table command (symbol) cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 notes rda (1st) l h mrs (2nd) l v v v v v 8 notes: 8. refer to ?mode register table?. auto-refresh command table pd function command (symbol) current state n ? 1n cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 notes active wra (1st) standby h h l l auto-refresh ref (2nd) active h h l self-refresh command table pd function command (symbol) current state n ? 1n cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 notes active wra (1st) standby h h l l self-refresh entry ref (2nd) active h l l 9, 10 self-refresh continue ? self-refresh l l self-refresh exit selfx self-refresh l h h 11 power down table pd function command (symbol) current state n ? 1n cs fn ba2~ba0 a13~a9 a8 a7 a6~a0 notes power down entry pden standby h l h 10 power down continue ? power down l l power down exit pdex power down l h h 11 notes: 9. pd has to be brought to low within t fpdl from ref command. 10. pd should be brought to low after dq?s state turned high impedance. 11. when pd is brought to high from low, this function is executed asynchronously.
tc59lm914/06amg-37,-50 2004-08-20 20/59 rev 1.0 function truth table (continued) pd current state n ? 1 n cs fn address command action notes h h h desl nop h h l h ba, ua rda row activate for read h h l l ba, ua wra row activate for write h l h pden power down entry 12 h l l ? illegal idle l ? refer to power down state h h h la lal begin read h h l op-code mrs/emrs access to mode register h l h pden illegal h l l mrs/emrs illegal row active for read l ? invalid h h h la lal begin write h h l ref auto-refresh h l h pden illegal h l l ref (self) self-refresh entry row active for write l ? invalid h h h desl continue burst read to end h h l h ba, ua rda illegal 13 h h l l ba, ua wra illegal 13 h l h pden illegal h l l ? illegal read l ? invalid h h h desl data write & continue burst write to end h h l h ba, ua rda illegal 13 h h l l ba, ua wra illegal 13 h l h pden illegal h l l ? illegal write l ? invalid h h h desl nop idle after i refc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h pden self-refresh entry 14 h l l ? illegal auto-refreshing l ? refer to self-refreshing state h h h desl nop idle after i rsc h h l h ba, ua rda illegal h h l l ba, ua wra illegal h l h pden illegal h l l ? illegal mode register accessing l ? invalid h ? invalid l l ? maintain power down mode l h h pdex exit power down mode idle after t pdex power down l h l ? illegal h ? invalid l l ? maintain self-refresh l h h selfx exit self-refresh idle after i refc self-refreshing l h l ? illegal notes: 12. illegal if any bank is not idle. 13. illegal to bank in specified stat es; function may be legal in the bank inidicated by bank address (ba). 14. illegal if t fpdl is not satisfied.
tc59lm914/06amg-37,-50 2004-08-20 21/59 rev 1.0 mode register table regular mode register (notes: 1) address ba1 * 1 ba0 * 1 ba2, a13~a8 a7 * 3 a6~a4 a3 a2~a0 register 0 0 0 te cl bt bl a7 test mode (te) a3 burst type (bt) 0 regular (default) 0 sequential 1 test mode entry 1 interleave a6 a5 a4 cas latency (cl) a2 a1 a0 burst length (bl) 0 0 reserved * 2 0 0 0 reserved * 2 0 1 0 reserved * 2 0 0 1 2 0 1 1 3 0 1 0 4 1 0 0 4 0 1 1 1 0 1 5 1 reserved * 2 1 1 0 reserved * 2 1 1 1 reserved * 2 extended mode register (notes: 4) address ba1 * 4 ba0 * 4 ba2, a13~a12 a11 * 6 a10 * 7 a9~a7 a6 a5~a2 a1 a0 * 5 register 0 1 0 0 dqs ocd dic 0 dic ds a9 a8 a7 driver impedance adjustment a6 a1 output drive impedance control (dic) 0 0 0 ocd calibration mode exit 0 0 normal output driver 0 0 1 drive (1) 0 1 strong output driver 0 1 0 drive (0) 1 0 weak output driver 1 0 0 adjust mode 1 1 full strength output driver 1 1 1 ocd calibration default a10 dqs enable a0 dll switch (ds) 0 disable 0 dll enable 1 enable 1 dll disable notes: 1. regular mode register is chosen using the combination of ba0 = 0 and ba1 = 0. 2. ?reserved? places in regular mode register should not be set. 3. a7 in regular mode register must be set to ?0? (low state). because test mode is specific mode for supplier. 4. extended mode register is chosen using the combination of ba0 = 1 and ba1 = 0. 5. a0 in extended mode register must be set to "0" to enable dll for normal operation. 6. a11 in extended mode register must be set to ?0?. 7. TC59LM914AMG, a10 in extended mode register is ignored. dqs is available only tc59lm906amg.
tc59lm914/06amg-37,-50 2004-08-20 22/59 rev 1.0 state diagram standby (idle) self- refresh power down pden ( pd = l) pdex ( pd = h) selfx ( pd = h) mode register auto- refresh active active (restore) read write (buffer) pd = l pd = h wra rda mrs ref command input lal a utomatic return the second command at active state must be issued 1 clock after rda or wra command input. lal
tc59lm914/06amg-37,-50 2004-08-20 23/59 rev 1.0 timing diagrams single bank read timing (cl = 3) cl k clk hi-z dq (output) bl = 2 i rc = 5 cycles hi-z cl = 3 command i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda lal desl rda lal rda lal desl desl i rc = 5 cycles address ua la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle i ras = 4 cycles bank add. #0 #0 #0 dqs/ dqs (output) hi-z dq (output) bl = 4 hi-z dqs/ dqs (output) rda ua #0 cl = 3 cl = 3 cl = 3 cl = 3 cl = 3 note : TC59LM914AMG doesn?t have dqs . q0 q1 q0 q1 q0 q1 q0 q1 q0 q1 q0 q2 q3 q2 q3 q1 q2
tc59lm914/06amg-37,-50 2004-08-20 24/59 rev 1.0 single bank read timing (cl = 4) cl k clk hi-z dq (output) bl = 2 i rc = 5 cycles hi-z cl = 4 command i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda lal desl rda lal rda lal desl desl i rc = 5 cycles address ua la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle i ras = 4 cycles bank add. #0 #0 #0 dqs/ dqs (output) cl = 4 cl = 4 hi-z dq (output) bl = 4 hi-z cl = 4 dqs/ dqs (output) cl = 4 cl = 4 rda ua #0 note : TC59LM914AMG doesn?t have dqs . q0 q1 q0 q1 q0 q0 q1 q0 q1 q0 q2 q3 q2 q3
tc59lm914/06amg-37,-50 2004-08-20 25/59 rev 1.0 single bank read timing (cl = 5) i rc = 6 cycles cl k clk hi-z dq (output) bl = 2 hi-z cl = 5 command i rc = 6 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda lal desl rda lal rda lal desl address ua la ua la ua la i ras = 5 cycles i rcd = 1 cycle i ras = 5 cycles i rcd = 1 cycle i rcd = 1 cycle bank add. #0 #0 #0 dqs/ dqs (output) cl = 5 hi-z dq (output) bl = 4 hi-z cl = 5 dqs/ dqs (output) cl = 5 desl note : TC59LM914AMG doesn?t have dqs . q0 q1 q0 q1 q0 q1 q0 q1 q2 q3 q2 q3
tc59lm914/06amg-37,-50 2004-08-20 26/59 rev 1.0 single bank write timing (cl = 3) cl k clk dqs/ dqs (input) dq (input) bl = 2 i rc = 5 cycles wl = 2 command i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal desl wra lal wra lal desl desl i rc = 5 cycles address la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle i ras = 4 cycles bank add. #0 #0 #0 d0 d1 dqs/ dqs (input) dq (input) bl = 4 d0 d1 d2 d3 d0 d1 d0 d1 d0 d1 d2 d3 wra ua #0 wl = 2 wl = 2 wl = 2 wl = 2 wl = 2 d0 d1 d2 d3 note : TC59LM914AMG doesn?t have dqs . ua
tc59lm914/06amg-37,-50 2004-08-20 27/59 rev 1.0 single bank write timing (cl = 4) cl k clk dqs/ dqs (input) dq (input) bl = 2 i rc = 5 cycles wl = 3 command i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal desl wra lal wra lal desl desl i rc = 5 cycles address ua la ua la ua la i ras = 4 cycles i rcd = 1 cycle i ras = 4 cycles i rcd = 1 cycle i rcd = 1 cycle i ras = 4 cycles bank add. #0 #0 #0 wl = 3 d0 d1 wl = 3 dqs/ dqs (input) dq (input) bl = 4 wl = 3 wl = 3 wl = 3 d2 d3 note : TC59LM914AMG doesn?t have dqs . d0 d1 d0 d1 d0 d1 d2 d3 d0 d1 d2 wra ua #0 d3 d0 d1
tc59lm914/06amg-37,-50 2004-08-20 28/59 rev 1.0 single bank write timing (cl = 5) i rc = 6 cycles cl k clk dqs/ dqs (input) dq (input) bl = 2 wl = 4 command i rc = 6 cycles wra lal desl wra lal wra lal desl address ua la ua la ua la i ras = 5 cycles i rcd = 1 cycle i ras = 5 cycles i rcd = 1 cycle i rcd = 1 cycle bank add. #0 #0 #0 wl = 4 dqs/ dqs (input) dq (input) bl = 4 desl d0 d1 d0 d1 wl = 4 wl = 4 d0 d1 d0 d1 d2 d3 d2 d3 0 1 2 3 5 6 7 8 9 10 11 12 13 14 15 4 note : TC59LM914AMG doesn?t have dqs .
tc59lm914/06amg-37,-50 2004-08-20 29/59 rev 1.0 single bank read-write timing (cl = 3) cl k clk hi-z dqs dq bl = 2 i rc = 5 cycles hi-z cl = 3 command i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda lal desl rda lal wra lal desl desl i rc = 5 cycles address ua la ua la ua la bank add. #0 #0 #0 dqs wl = 2 cl = 3 hi-z dqs dq bl = 4 hi-z wra ua #0 cl = 3 wl = 2 cl = 3 hi-z hi-z note : TC59LM914AMG doesn?t have dqs . dqs q0 q1 d0 d1 q0 q1 d0 d1 q2 q3 d2 d3 q0 q1 q0 q1 q2
tc59lm914/06amg-37,-50 2004-08-20 30/59 rev 1.0 single bank read-write timing (cl = 4) cl k clk hi-z dqs dq bl = 2 i rc = 5 cycles hi-z cl = 4 command i rc = 5 cycles 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda lal desl rda lal wra lal desl desl i rc = 5 cycles address ua la ua la ua la bank add. #0 #0 #0 dqs wl = 3 cl = 4 hi-z dqs dq bl = 4 hi-z cl = 4 dqs wl = 3 cl = 4 wra ua #0 hi-z hi-z note : TC59LM914AMG doesn?t have dqs . q0 q1 d0 d1 q0 q0 q1 d0 d1 q2 q3 d2 d3 q0
tc59lm914/06amg-37,-50 2004-08-20 31/59 rev 1.0 single bank read-write timing (cl = 5) cl k clk dqs dq bl = 2 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 address bank add. dqs dqs dq bl = 4 dqs i rc = 6 cycles hi-z hi-z cl = 5 i rc = 6 cycles rda lal rda lal wra lal desl ua la ua la ua la #0 #0 #0 wl = 4 hi-z hi-z cl = 5 desl wl = 4 hi-z hi-z note : TC59LM914AMG doesn?t have dqs . q0 q1 d0 d1 q0 q1 q2 q3 d0 d1 d2 d3 desl
tc59lm914/06amg-37,-50 2004-08-20 32/59 rev 1.0 multiple bank read timing (cl = 3) rda ua bank "b" clk clk hi-z dq (output) bl = 2 i rbd = 2 cycles hi-z cl = 3 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lal rda rda lal rda lal address ua la ua la ua la bank add. bank "a" dqs/ dqs (output) cl = 3 dq (output) bl = 4 hi-z dqs/ dqs (output) rda lal desl i rbd = 2 cycles rda lal rda i rbd = 2 cycles i rbd = 2 cycles lal rda lal ua la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles hi-z note: l rc to the same bank must be satisfied. TC59LM914AMG doesn?t have dqs . i rbd = 2 cycles la cl = 3 cl = 3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2 qc3 qd0 qa0 qa1 qb0 qb1 qa0 qa1 qb0 qb1 qc0 qc1 qd0 qd1 qd1
tc59lm914/06amg-37,-50 2004-08-20 33/59 rev 1.0 multiple bank read timing (cl = 4) rda ua bank "b" cl k clk hi-z dq (output) bl = 2 i rbd = 2 cycles hi-z cl = 4 command 0 1 23 4 56789101112 13 1415 lal rda rda lal rda lal address ua la ua la ua la bank add. bank "a" dqs/ dqs (output) cl = 4 dq (output) bl = 4 hi-z dqs/ dqs (output) rda lal desl i rbd = 2 cycles rda lal rda i rbd = 2 cycles i rbd = 2 cycles lal rda lal ua la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles hi-z cl = 4 cl = 4 note: l rc to the same bank must be satisfied. TC59LM914AMG doesn?t have dqs . i rbd = 2 cycles la qa0 qa1 qb0 qb1 qa0 qa1 qb0 qb1 qc0 qc1 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 qc0 qc1 qc2
tc59lm914/06amg-37,-50 2004-08-20 34/59 rev 1.0 multiple bank read timing (cl = 5) cl k clk dq (output) bl = 2 hi-z cl = 5 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 rda lal rda lal rda address ua la ua la ua bank add. bank "a" dqs/ dqs (output) cl = 5 dq (output) bl = 4 hi-z dqs/ dqs (output) rda lal lal rda lal rda lal rda ua la la ua la ua la ua bank "b" bank "a" bank "b" bank "c" bank "d" i rc (bank"a") = 6 cycles i rc (bank"b") = 6 cycles hi-z hi-z cl = 5 cl = 5 desl bank "a" i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles lal la note: l rc to the same bank must be satisfied. TC59LM914AMG doesn?t have dqs . qa0qa1qa2qa3qb0qb1qb2qb3 qa0 qa1 qa2 qa3qb0qb1qb2 qa0qa1 qb0qb1 qa0 qa1 qb0qb1
tc59lm914/06amg-37,-50 2004-08-20 35/59 rev 1.0 multiple bank write timing (cl = 3) clk clk dqs/ dqs (input) dq (input) bl = 2 wl = 2 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lal wra wra lal wra lal address ua la ua la ua la bank add. bank "a" wl = 2 dqs/ dqs (input) dq (input) bl = 4 wra lal desl wra lal wra lal wra lal ua la ua la ua la ua la bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles db0 db1 da0 da1 db0 db1 dc0 dc1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 dc2 dc3 note: l rc to the same bank must be satisfied. TC59LM914AMG doesn?t have dqs . i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 dd0 dd1 dd0 dd1 wra ua bank "b" wl = 2 wl = 2 dd2 dd3
tc59lm914/06amg-37,-50 2004-08-20 36/59 rev 1.0 multiple bank write timing (cl = 4) clk clk dqs/ dqs (input) dq (input) bl = 2 wl = 3 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 lal wra wra lal wra lal address ua la ua la ua la bank add. bank "a" wl = 3 dqs/ dqs (input) dq (input) bl = 4 wra lal desl wra lal wra lal wra lal ua la ua la ua la ua la bank "b" bank "a" bank "b" bank "c" bank "d" bank "a" i rc (bank"a") = 5 cycles i rc (bank"b") = 5 cycles db0 db1 da0 da1 db0 db1 dc0 dc1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 dc2 dc3 note: l rc to the same bank must be satisfied. TC59LM914AMG doesn?t have dqs . i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 dd0 dd1 wl = 3 wl = 3 dd0 dd1 wra ua bank "b"
tc59lm914/06amg-37,-50 2004-08-20 37/59 rev 1.0 multiple bank write timing (cl = 5) cl k clk dqs/ dqs (input) dq (input) bl = 2 wl = 4 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 address bank add. wl = 4 dqs dqs (input) dq (input) bl = 4 i rc (bank"a") = 6 cycles i rc (bank"b") = 6 cycles db0 db1 da0 da1 db0 db1 dc0 dc1 da0 da1 da2 da3 db0 db1 db2 db3 da0 da1 da2 da3 db0 db1 db2 db3 dc0 dc1 note: l rc to the same bank must be satisfied. TC59LM914AMG doesn?t have dqs . i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles i rbd = 2 cycles da0 da1 wl = 4 wl = 4 wra lal wra lal wra wra lal lal wra lal wra lal wra desl lal ua la ua la ua la ua la ua la ua la ua la bank "a" bank "b" bank "a" bank "b" bank "c" bank "d" bank "a"
tc59lm914/06amg-37,-50 2004-08-20 38/59 rev 1.0 multiple bank read-write timing (bl = 2) cl k clk dqs cl = 4 i rbd = 2 cycles wl = 3 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 address bank add. cl = 4 i rc (bank"a") i rc (bank"b") dqs dq hi - z dqs cl = 5 wl = 4 dqs cl = 5 note: l rc to the same bank must be satisfied. TC59LM914AMG doesn?t have dqs . dqs cl = 3 wl = 2 cl = 3 dqs hi - z dq hi - z hi - z hi - z i wrd = 1 cycle i rwd = = 1 cycle i rwd = 2 cycles i wrd = =
tc59lm914/06amg-37,-50 2004-08-20 39/59 rev 1.0 multiple bank read-write timing (bl = 4) cl k clk dqs cl = 4 i rbd = 2 cycles wl = 3 command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 address bank add. cl = 4 i rc (bank"a") i rc (bank"b") i wrd = 1 cycle i rwd = 3 cycles i wrd = = = 5 wl = 4 dqs cl = 5 hi - z dq hi - z note: l rc to the same bank must be satisfied. TC59LM914AMG doesn?t have dqs . i wrd = 1 cycle dqs cl = 3 wl = 2 cl = 3 dqs hi - z dq hi - z hi - z hi - z i wrd = 1 cycle i rwd =
tc59lm914/06amg-37,-50 2004-08-20 40/59 rev 1.0 write with variavle write length (vw) control (cl = 4) cl k clk dqs/ dqs (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 wra lal wra lal desl address ua la=#3 vw=all ua bank add. bank "a" bank "a" bl = 2, sequential mode desl la=#1 vw=1 vw0 = low vw1 = don't care vw0 = high vw1 = don't care dq (input) d0 d0 d1 lowe r address #3 #2 #1 ( #0 ) last one data is masked. dqs/ dqs (input) command wra lal wra lal desl address ua la=#3 vw=all ua bank add. bank "a" bank "a" bl = 4, sequential mode desl la=#1 vw=1 dq (input) d0 d0 d1 lower address #3 #0 #1 ( #2 )( #3 )( #0 ) last three data are masked. desl wra lal vw0 = high vw1 = low vw0 = high vw1 = high ua la=#2 vw=2 vw0 = low vw1 = high bank "a" d2 d3 d0 d1 #1 #2 last two data are masked. ( #0 )( #1 ) #2 #3 note: dqs ( dqs ) input must be continued till end of burst count even if some of laster data is masked.
tc59lm914/06amg-37,-50 2004-08-20 41/59 rev 1.0 power down timing (cl = 4, bl = 4) read cycle to power down mode clk clk 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 i pda t ih t is i pd = 1 cycle t pdex power down entry power down exit note: pd must be kept "high" level until end of burst data output. pd should be brought to "high" within t refi (max.) to maintain the data written into cell. in power down mode, pd "low" and a stable clock signal must be maintained. when pd is brought to "high", a valid executable command may be applied l pda cycles later. TC59LM914AMG doesn?t have dqs . dqs (output) command rda lal desl address ua ua desl rda or wra la l rc(min) , t refi(max) t qpdh dqs (output) hi-z hi-z cl = 4 hi-z hi-z dq (output) pd hi-z q0 q1 q2 q3
tc59lm914/06amg-37,-50 2004-08-20 42/59 rev 1.0 power down timing (cl = 4, bl = 4) write cycle to power down mode clk clk 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 i pda t ih t is i pd = 1 cycle t pdex note: pd must be kept "high" level until wl+2 clock cycles from lal command. pd should be brought to "high" within t refi (max.) to maintain the data written into cell. in power down mode, pd "low" and a stable clock signal must be maintained. when pd is brought to "high", a valid executable command may be applied l pda cycles later. TC59LM914AMG doesn?t have dqs . dqs (input) command wra lal desl address ua ua desl rda or wra la l rc(min) , t refi(max) dqs (input) wl = 3 d0 d1 d2 d3 dq (input) pd 2 clock cycles wl = 3
tc59lm914/06amg-37,-50 2004-08-20 43/59 rev 1.0 mode register set timing (cl = 4, bl = 2) from read operation to mode register set operation. cl k clk dqs (output) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rda lal rda mrs desl a13~a0 ua valid (opcode) dqs i rsc desl rd a or wr a la ua ba0~ba2 ba ba0="0" ba1="0" ba2="0" ba lal dq (output) cl + bl/2 hi-z q0 q1 note: minimum delay from lal following rda to rda of mrs operation is cl+bl/2. TC59LM914AMG doesn?t have dqs . 15 la hi-z
tc59lm914/06amg-37,-50 2004-08-20 44/59 rev 1.0 mode register set timing (cl = 4, bl = 4) from write operation to mode register set operation. cl k clk dqs (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 wra lal rda mrs desl a13~a0 ua valid (opcode) dqs (input) i rsc desl rd a or wr a la ua ba0~ba2 ba ba0="0" ba1="0" ba2="0" ba d0 d1 d2 d3 dq (input) 15 wl+bl/2 la lal note: minimum delay from lal following wra to rda of mrs operation is wl+bl/2. TC59LM914AMG doesn?t have dqs .
tc59lm914/06amg-37,-50 2004-08-20 45/59 rev 1.0 extended mode register set timing (cl = 4, bl = 2) from read operation to extended mode register set operation. cl k clk dqs (output) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 rda lal rda mrs desl a13~a0 ua valid (opcode) dqs (output) i rsc desl rd a or wr a la ua ba0~ba2 ba ba0="1" ba1="0" ba2="0" ba dq (output) cl + bl/2 hi-z q0 q1 note: minimum delay from lal following rda to rda of emrs operation is cl+bl/2. dll switch in extended mode register must be set to enable mode for normal operation. dll lock-on time is needed after initial emrs operation. see power up sequence. TC59LM914AMG doesn?t have dqs . 15 la lal hi-z
tc59lm914/06amg-37,-50 2004-08-20 46/59 rev 1.0 extended mode register set timing (cl = 4, bl = 4) from write operation to extende d mode register set operation. cl k clk dqs (input) command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 wra lal rda mrs desl a13~a0 ua valid (opcode) dqs (input) wl+bl/2 i rsc desl rd a or wr a la ua ba0~ba2 ba ba0="1" ba1="0" ba2="0" ba d0 d1 d2 d3 dq (input) note: dll switch in extended mode register must be set to enable mode for normal operation. dll lock-on time is needed after initial emrs operation. see power up sequence. minimum delay from lal following wra to rda of emrs operation is wl+bl/2. TC59LM914AMG doesn?t have dqs . 15 lal la
tc59lm914/06amg-37,-50 2004-08-20 47/59 rev 1.0 auto-refresh timing (cl = 4, bl = 4) cl k wra ref wra ref wra ref wra ref wra ref t 1 t 2 t 3 t 7 t 8 8 refresh cycle t refi = total time of 8 refresh cycle 8 t 1 + t 2 + t 3 + t 4 + t 5 + t 6 + t 7 + t 8 8 = t refi is specified to avoid partly concentrated current of refresh operation that is activated larger area than read / write operation. cl k clk hi-z dqs/ dqs (output) dq (output) 0 1 2 3 4 5 6 7 n ? 1n n + 1 n + 2 rda lal hi-z hi-z cl = 4 command i rc = 5 cycles desl rd a or wr a lal o r mrs or ref i rcd = 1 cycle note: in case of cl = 4, i refc must be meet 18 clock cycles. when the auto-refresh operation is performed, the synthetic average interval of auto-refresh command specified by t refi must be satisfied. t refi is average interval time in 8 refr esh cycles that is sampled randomly. TC59LM914AMG doesn?t have dqs . wra ref i refc = 18 cycles hi-z i ras = 4 cycles i rcd = 1 cycle desl bank, ua la bank, address q0 q1 q2 q3
tc59lm914/06amg-37,-50 2004-08-20 48/59 rev 1.0 self-refresh entry timing self-refresh exit timing notes: 1. is don?t care. 2. clock should be stable prior to pd = ?high? if clock input is suspended in self-refresh mode. 3. desl command must be asserted during i refc after pd is brought to ?high?. 4. i pda is defined from the fi rst clock rising edge after pd is brought to ?high?. 5. it is desirable that one auto-refresh command is issued just after self-refresh exit before any other operation. 6. any command (except read command) can be issued after i refc . 7. read command (rda + lal) can be issued after i lock . 8. TC59LM914AMG doesn?t have dqs . cl k clk hi-z dqs/ dqs (output) dq (output) 0 1 2 m ? 1mm + 1m + 2 hi-z command i lock t pdex i pd a = * 4 pd desl * 3 lal * 7 wra * 5 ref * 5 desl rda * 7 n ? 1nn + 1 p ? 1 p command (1st) * 6 command (2nd) * 6 i rcd = * 2 i refc i refc i rcd = ? 1mm + 1 wra ref qx hi-z command i rcd = 1 cycle i refc desl t fpdl (min) t fpdl (max) i pdv * 2 pd i ckd t qpdh auto refresh self refresh entry
tc59lm914/06amg-37,-50 2004-08-20 49/59 rev 1.0 functional description network fcram tm fcram tm is an acronym of fast cycle ra ndom access memory. the network fcram tm is competent to perform fast random core access, low latency and high-speed data transfer. pin functions clock inputs: clk & the clk and clk inputs are used as the reference for synchron ous operation. clk is ma ster clock input. the cs , fn and all address input signals are sampled on the cro ssing of the positive edge of clk and the negative edge of clk . the dqs and dq output are aligned to the crossing point of clk and clk . the timing reference point for the differential clock is when the clk and clk signals cross during a transition. power down: the pd input controls the entry to the power down or self-refresh modes. the pd input does not have a clock suspend function like a cke inpu t of a standard sdrams, ther efore it is illegal to bring pd pin into low state if any read or write operation is being performed. chip select & function control: & fn the cs and fn inputs are a control signal fo r forming the operation commands on fcram tm . each operation mode is decided by the combination of the two consecutive operat ion commands using the cs and fn inputs. bank addresses: ba0~ba2 the ba0 to ba2 inputs are latched at the time of asse rtion of the rda or wra command and are selected the bank to be used for the operation. ba0 and ba1 also define which mode register is loaded during the mode register set command (mrs or emrs). ba0 ba1 ba2 bank #0 0 0 0 bank #1 1 0 0 bank #2 0 1 0 bank #3 1 1 0 bank #4 0 0 1 bank #5 1 0 1 bank #6 0 1 1 bank #7 1 1 1 also, when ba2 input assign to a14 input, tc59lm914/06amg can function as 4 bank devices and can keep backward compatibility to 25 6mb (4bank) network fcram. address inputs: a0~a13 address inputs are used to access the arbitrary addr ess of the memory cell array within each bank. the upper addresses with bank addresses are latched at the rda or wra command and the lower addresses are latched at the lal command. the a0 to a13 inputs are also used for setting the data in the regular or extended mode register set cycle. i/o organization upper address lower address 8 bits a0~a13 a0~a8 8 bank operation 16 bits a0~a13 a0~a7 8 bits a0~a13, ba2(a14) a0~a8 4 bank operation 16 bits a0~a13, ba2(a14) a0~a7 clk pd cs
tc59lm914/06amg-37,-50 2004-08-20 50/59 rev 1.0 data input/output: dq0~dq7 or dq15 the input data of dq0 to dq15 are take n in synchronizing with the both edges of dqs in put signal. the output data of dq0 to dq15 are outputted synchronizin g with the both edges of dqs output signal. data strobe: dqs, dqs the dqs is bi-directional signal. both edge of dqs are used as the referenc e of data input or output. in write operation, the dqs used as an input si gnal is utilized for a latch of write da ta. in read operation, the dqs is an output signal provides the read data strobe. tc59lm906amg has differential data strobe pin ( dqs ). when dqs is enable mode, dqs is differential output signal for dqs in read operation, data input are latched at the crossing point of dqs and dqs in write operation. when dqs is disable mode, dqs is always hi-z, and data input ar e latched at the crossing point of dqs and vref level. dqs mode is set at extended mode register set cycle. TC59LM914AMG doesn?t have dqs pin. data input are latched at th e crossing point of l/udqs and vref level in write operation. ldqs is strobe signal for dq0-dq7. udqs is stro be signal for dq8-dq15. power supply: v dd , v ddq , v ss , v ssq v dd and v ss are power supply pins for memory core and peripheral circuits. v ddq and v ssq are power supply pins for the output buffer. reference voltage: v ref v ref is reference voltage for all input signals.
tc59lm914/06amg-37,-50 2004-08-20 51/59 rev 1.0 command functions and operations tc59lm914/06amg are introduced the two consecutive co mmand input method. therefore, except for power down mode, each operation mode decided by the combinat ion of the first command and the second command from stand-by states of the bank to be accessed. read operation (1st command + 2nd command = rda + lal) issuing the rda command with bank addresses and upper addresses to the idle bank puts the bank designated by bank address in a read mode. when the lal command with lower addresses is issued at the next clock of the rda command, the data is read out sequ entially synchronizing with the both edges of dqs/ dqs output signal (burst read operation). the initial valid read data appears after cas latency from the issuing of the lal command. the valid data is outputted for a burst length. the cas latency, the burst length of read data and the burst type must be set in the mode register beforehand. the read operated bank goes back automatically to the idle state after l rc . dqs is differential data strobe signal supported tc59lm906amg. write operation (1st command + 2nd command = wra + lal) issuing the wra command with bank addresses and upper addresses to the idle bank puts the bank designated by bank address in a write mode. when the lal command with lower addresses is issued at the next clock of the wra command, the input data is latche d sequentially synchronizing with the both edges of dqs/ dqs input signal (burst write operation). the data and dqs/ dqs inputs have to be asserted in keeping with clock input after cas latency-1 from the issuing of the lal command. the dqs/ dqs has to be provided for a burst length. the cas latency and the burst type must be set in the mode register beforehand. the write operated bank goes back automatically to the idle state after l rc . write burst length is controlled by vw0 and vw1 inputs with lal command. see vw truth table. dqs is differential data strobe signal supported tc59lm906amg. auto-refresh operation (1st command + 2nd command = wra + ref) tc59lm914/06amg are required to refresh like a standard sdram. the auto-refresh operation is begun with the ref command following to the wra command. the auto-r efresh mode can be effective only when all banks are in the idle state. in a point to notice, the write mo de started with the wra command is canceled by the ref command having gone into the next clock of the wra command instead of the lal command. the minimum period between the auto-refresh command and the next command is specified by l refc . however, about a synthetic average interval of auto-refresh command, it must be careful. in case of equally distributed refresh, auto-refresh command has to be issued within once for every 3.9 s by the maximum. in c ase of burst refresh or random distributed refresh, the average interval of eight consecutive auto-refresh command has to be more than 400 ns always. in other words, the number of auto-refresh cycles that be performed within 3.2 s (8 400 ns) is to 8 times in the maximum. self-refresh operation (1st command + 2nd command = wra + ref with = ?l?) in case of self-refresh operation, refresh operation can be performed automatically by using an internal timer. when all banks are in the idle state and all outputs are in hi-z states, the tc59lm914/06amg become self-refresh mode by issuing the self-refresh command. pd has to be brought to ?low? within t fpdl from the ref command following to the wra command for a self-refresh mode entry. in order to satisfy the refresh period, the self-refresh entry command should be asserted within 3.9 s after the latest auto-refresh command. once the device enters self-refresh mode, the desl command must be continued for l refc period. in addition, it is desirable that clock input is kept in l ckd period. the device is in self-refresh mode as long as pd held ?low?. during self-refresh mode, all input and output buffers are disabled except for pd , therefore the power dissipation lowers. regarding a self-refresh mode exit, pd has to be changed over from ?low? to ?high? along with the desl command, and the desl command has to be continuously issued in the number of clocks specified by l refc . the self-refresh exit function is asynchronous operation. it is required that one auto-refresh command is issued to avoid the violatio n of the refresh period just after l refc from self-refresh exit. power down mode ( = ?l?) when all banks are in the idle state and dq outputs are in hi-z states, the tc59lm914/06amg become power down mode by asserting pd is ?low?. when the device enters th e power down mode, all input and output buffers are disabled after specified time except for pd . therefore, the power dissipation lowers. to exit the power down mode, pd has to be brought to ?high? and the desl command has to be issued for two clock cycle after pd goes high. the power down exit function is asynchr onous operation. pd pd
tc59lm914/06amg-37,-50 2004-08-20 52/59 rev 1.0 mode register set (mrs) and extended mode register set (emrs) (1st command + 2nd command = rda + mrs) when all banks are in the idle state, issuing the mrs command following to the rda command can program the mode register. in a point to notice, the read mode started with the rda command is canceled by the mrs command having gone into the next clock of the rda co mmand instead of the lal command. the data to be set in the mode register is transferred using a0 to a13, ba0 to ba2 address inputs. the tc59lm914/06amg have two mode registers. these are regular and extended mode register. the regular or extended mode register is chosen by ba0 and ba1 in the mrs co mmand. the regular mode register designates the operation mode for a read or write cycle. the regular mode register has four function fields. the four fields are as follows: (r-1) burst length field to set the length of burst data (r-2) burst type field to designate the lower address access sequence in a burst cycle (r-3) cas latency field to set the access time in clock cycle (r-4) test mode field to use for supplier only. the extended mode register has four function fields. the five fields are as follows: (e-1) dll switch field to choose either dll enable or dll disable. (e-2) output driver im pedance control field. (e-3) off-chip driver (ocd) impedance adju stment for full strength output driver. (e-4) dqs enable field. once those fields in the mode register are set up, the register contents are mainta ined until the mode register is set up again by another mrs command or power supply is lost. the initial value of the regular or extended mode register after power-up is undefined, therefore th e mode register set command must be issued before proper operation. ? regular mode register/extended mode register change bits (ba0, ba1) these bits are used to choose eith er regular mrs or extended mrs ba1 ba0 mode register set 0 0 regular mrs 0 1 extended mrs 1 reserved regular mode register fields (r-1) burst length field (a2 to a0), (bl) this field specifies the data length for column access using the a2 to a0 pins and sets the burst length to be 2 or 4 words. a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 reserved 1 reserved (r-2) burst type field (a3), (bt) the burst type can be chosen interleave mode or se quential mode. when the a3 bit is ?0?, sequential mode is selected. when the a3 bit is ?1?, interlea ve mode is selected. both burst types support burst length of 2 and 4 words. a3 burst type 0 sequential 1 interleave
tc59lm914/06amg-37,-50 2004-08-20 53/59 rev 1.0 ? addressing sequence of sequential mode a column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. addressing sequence for sequential mode data access address burst length data 0 n data 1 n + 1 data 2 n + 2 data 3 n + 3 2 words (address bits is la0) not carried from la0~la1 4 words (address bits is la1, la0) not carried from la1~la2 ? addressing sequence of interleave mode a column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. addressing sequence for interleave mode data access address burst length data 0 ??? a8 a7 a6 a5 a4 a3 a2 a1 a0 data 1 ??? a8 a7 a6 a5 a4 a3 a2 a1 0 a data 2 ??? a8 a7 a6 a5 a4 a3 a2 1 a a0 data 3 ??? a8 a7 a6 a5 a4 a3 a2 1 a 0 a 2 words 4 words (r-3) cas latency field (a6 to a4), (cl) this field specifies the number of clock cycles from the assertion of the lal command following the rda command to the first data read. the minimum values of cas latency depends on the frequency of clk. in a write mode, the place of clock that should input write data is cas latency cycles ? 1. a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 reserved 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 reserved 1 1 1 reserved (r-4) test mode field (a7), (te) this bit is used to enter test mode for supplier only and must be set to ?0? for normal operation. (r-5) reserved field in the regular mode register ? reserved bits (a8 to a13, ba2) these bits are reserved for future operations. th ey must be set to ?0? for normal operation. cl k clk command dqs/ dqs dq data 0 data 1 data 2 data 3 rda lal cas latency = 4
tc59lm914/06amg-37,-50 2004-08-20 54/59 rev 1.0 extended mode register fields (e-1) dll switch field (a0), (ds) this bit is used to enable dll. when the a0 bit is se t ?0?, dll is enabled. this bit must set to ?0? for normal operation. (e-2) output driver impedance control field (a1, a6) (dic) this field is used to choose outp ut driver strength. four types of driver strength are supported. output driver strength can be set by field in emrs with ocd calibration defa ult (a7~a9=1 at emrs). a6 a1 output driver impedance control 0 0 normal output driver 0 1 strong output driver 1 0 weak output driver 1 1 full strength output driver (e-3) off-chip driver (ocd) impeda nce adjustment for full strength output driver (a7 to a9) (ocd) output driver strength can be set by dic field (e-2). in case of choosing full strength output driver, ocd calibration is available. the driver strength se t by dic field is the initial driver level at ocd impedance adjustment. when ocd calib ration is performed, a1 and a6 inputs at emrs must be ?1? for full strength output driver. the network fcram tm supports driver calibration feature and the flow chart below is an example of sequence. every calibration mode command should be followed by ?ocd calibration mode exit? before any other command being issued. mrs should be set before entering ocd impedance adjustment. emrs: ocd calibration mode exit mrs should be set before entering ocd impedance adjustment. emrs: drive(1) dq &dqs high; dqs low te s t start emrs: ocd calibration mode exit emrs: enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: ocd calibration mode exit emrs: drive(0) dq &dqs low; dqs high a ll ok te s t emrs: ocd calibration mode exit emrs: enter adjust mode bl=4 code input to all dqs inc, dec, or nop emrs: ocd calibration mode exit a ll ok need calibration need calibration emrs: ocd calibration mode exit end
tc59lm914/06amg-37,-50 2004-08-20 55/59 rev 1.0 extended mode register set for ocd impedance adjustment ocd impedance adjustment can be done using the fo llowing emrs mode. in drive mode all outputs are driven out by network fcram. in drive (1) mo de, all dq, dqs signals are driven high and dqs signals are driven low. in drive (0) mode, all dq, dqs signals are driven low and dqs signals are driven high. in adjust mode, bl=4 of operation code data must be used a9 a8 a7 operation 0 0 0 ocd calibration mode exit 0 0 1 drive (1) dq, dqs high and dqs low 0 1 0 drive (0) dq, dqs low and dqs high 1 0 0 adjust mode 1 1 1 ocd calibration default ocd impedance adjust to adjust output driver impedance, controllers must issue the adjust emrs command along with a 4bit burst code to network fcram. for this operation, bu rst length has to be set to bl=4 via mrs command before activating ocd and controllers must drive this burst code to all dqs at the same time. dt0 means all dq bits at bit time 0, dt1 at bit time 1, and so forth. the driver output impedance is adjusted for all dqs simultaneously and after ocd calibration, all dqs of a given network fcram will be adjusted to the same driver strength setting. the maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. off-chip driver program 4bit burst code inputs to all dqs operation d t0 d t1 d t2 d t3 pull-up driver strength pull-down driver strength 0 0 0 0 nop (no operation) nop (no operation) 0 0 0 1 increase by 1 step nop 0 0 1 0 decrease by 1 step nop 0 1 0 0 nop increase by 1 step 1 0 0 0 nop decrease by 1 step 0 1 0 1 increase by 1 step increase by 1 step 0 1 1 0 decrease by 1 step increase by 1 step 1 0 0 1 increase by 1 step decrease by 1 step 1 0 1 0 decrease by 1 step decrease by 1 step other combinations reserved for proper operation of adjust mode, wl=cl-1 clocks and t ds / t dh should be met as the following timing diagram. for input data pattern for adjustment, dt0~dt3 is a fixed order and ?not affected by mrs addressing mode (i.e. sequential or interleave). driver strength is controlled within the fo llowing range by ocd impedance adjustment. symbol parameter min max unit notes i oh (dc) output source dc current for v dd q = 1.7v~1.9v v dd q = 1.7v v oh = 1.420v ? 14.0 ? 18.7 i ol (dc) full strength output driver output sink dc current for v dd q = 1.7v~1.9v v dd q = 1.7v v ol = 0.280v 14.0 18.7 ma
tc59lm914/06amg-37,-50 2004-08-20 56/59 rev 1.0 drive mode drive mode, both drive (1) and drive (0), is used for controllers to measure network fcram driver impedance. in this mode, al l outputs are driven out t oit after ?enter drive mode? command and all output drivers are turned-off t oit after ?ocd calibration mode exit? command as the following timing diagram. (e-4) dqs enable field (a10), ( dqs ) this bit is used to enable differential data strobe. dqs is available on tc59lm906amg. this field of TC59LM914AMG is ignored. a10 dqs enable 0 disable 1 enable (e-5) interface mode select (a11) this bit must be always set ?0?. (e-6) reserved field (a2 to a5, a12 to a13, ba2) these bits are reserved for future operations and must be set to ?0? for normal operation. command rda emrs ocd adjust mode nop nop nop nop rda emrs nop dqs_in dq_in d t0 d t1 d t2 d t3 dqs t ds t dh clk clk ocd calibration mode exit wl 1clock command enter drive mode dqs, dqs dq clk clk ocd calibration mode exit rda emrs nop nop rda emrs nop t oit t oit dqs high for drive (1), dqs low for drive (0) dqs high & dqs low for drive (1), dqs low & dqs high for drive (0) 0 12ns 0 12ns
tc59lm914/06amg-37,-50 2004-08-20 57/59 rev 1.0 package dimensions 0.2 s b 0.2 s a 0.08 s ab 13.086 0 -0.15 16.5 10.975 0 -0.15 12.7 0.15 0.1 0.2 s 0.15min 1.20max 0.4 0.05 1.5 1.5 123 456 index r p n m l k j h g f e d c b a 1.0 2.0 1.25 3.85 3.85 1.85 1.0 a b s s 0.5 0.05 p-bga64-1317-1.00az note: in order to support a package, four outer balls located on f and k row are required to assembly to board. these four ball is not connected to any electrical level. weight: 0.23g (typ.)
tc59lm914/06amg-37,-50 2004-08-20 58/59 rev 1.0 revision history ? rev.0.9 (feb. 27 ?2004) ? rev0.91 (mar. 16 ?2004) ? corrected typo (page57). pin name is changed from ?q? to ?r?. ? rev0.92 (apr. 21 ?2004) ? parameter definition in recommended dc, ac op erating conditions table are changed (page 5). ? v ick (dc): differential clock dc input voltage ? v id (dc): input dc differential volt age. clk and /clk inputs (dc) ? v id (ac): input ac differential voltage. clk and /clk inputs (ac) ? v id (ac),min is changed from 0.55v to 0.5v. ? v iso (ac): differential clock ac middle level. ? clk is changed to v tr and clk is changed to v cp (page 6). ? below comment is added in note(10) (page 6). vtr is the true input (such as clk, dqs) leve l and vcp is the complementary input (such as clk , dqs ) level. ? rev0.93 (jun. 9 ?2004) ? package name (p ? bga64 ? 1317 ? 1.00az) added (page 1). ? t refi (auto-refresh average interval) spec changed from 7.8 s to 3.9 s (page 1, 10, 51). ? v dd range changed from 2.5v 0.15v to 2.5v 0.125v. ? corrected typo (page 9, 10, 14, 15, 17) ? t dsp spec changed for all speed bin as below (page 9) t dsp(min) = 0.4 t ck 0.35 t ck t dsp(max) = 0.6 t ck 0.65 t ck ? t is and t ih spec changed for all speed bin as below (page 9) ? ? 37?: t is = 0.6ns 0.5ns , t ih = 0.6ns 0.5ns ? ? 45?: t is = 0.7ns 0.6ns , t ih = 0.7ns 0.6ns ? ? 50?: t is = 0.8ns 0.7ns , t ih = 0.8ns 0.7ns ? t dsh (dqs input falling edge hold time from clk) added (page 9). ? t oit (ocd drive mode output de lay time) added (page 10, 56). ? ocd definition at power up sequence added (page 12). ? note (4) added at power up sequence (page 12). ? ocd setting on extended mode register table changed as below (page 21, 54, 55) (a9, a8, a7) = (0, 0, 0): ocd calibration default ocd calibration mode exit. (a9, a8, a7) = (1, 1, 1): ocd calibration mode exit ocd calibration mode default. ? full strength output driver added on dic (page 21, 54). (a6, a1) = (1, 1): reserved full strength output driver. ? note (5) added on self-refresh entry timing (page 48). ? explanation for ocd impedance adjustment modified (page 54). ? i oh / i ol table added (page 55). ? rev1.0 (aug. 20 ?2004) ? ?-45? version dropped. ? some notes in the page 8 moved to page 7 (page 7, 8). ? note 2 changed as below (page 7). before: these parameters depend on the output load ing. the specified values are obtained with the output open after: these parameters define the current between v dd and v ss . ? corrected typo (page 2, 3, 14, 15, 17). ? package weight (0.23g) added (page 57).
tc59lm914/06amg-37,-50 2004-08-20 59/59 rev 1.0 ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inhe rent electrical sensitivity and vulnerability to physical stress. it is the responsibility of t he buyer, when utilizing toshiba products , to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshi ba products specifications. also, pl ease keep in mind the precautions and conditions set forth in the ?handling guide for semicond uctor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are inte nded for usage in general electronics applications (computer, personal equipment, office equipment, measuri ng equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunc tion or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traffic signa l instruments, combusti on control instruments, medical instruments, all types of safety devices, et c.. unintended usage of toshiba products listed in this document shall be made at th e customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intelle ctual property or other rights of the third parties which may re sult from its use. no license is grant ed by implication or otherwise under any intellectual property or other right s of toshiba corporation or others. ? the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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